1. Field of the Invention
The field of the invention relates generally to phase locked frequency synthesizers, and more particularly, to an apparatus and method to reduce the spurious sidebands in phase locked loops including integer and fractional phase locked loop synthesizers.
2. Description of the Related Art
Many modulation, detection, and frequency-synthesis methods, long recognized but difficult to implement, have become practical with the introduction of IC versions of the phase-locked loop (PLL). A simplified account of a PLL is a negative feedback system that maintains a constant phase and zero frequency difference between a reference frequency (F.sub.r) and a variable frequency. There are many circuits commonly used as phase detectors in typical industry practice. Description of available types and their operation can be found in Phase-Locked Loops Theory, Design and Applications, authored by Roland E. Best, 1993, pps. 93-104 and in Frequency Synthesis by Phase Lock, authored by William Egan, 1990, pps. 98-123 (ISBN 0-89464-456-4), which are incorporated herein by reference. One type of phase detector is the linear mixer phase detector, in which two sinusoidal inputs are multiplied to output a sine wave whose frequency is the difference between the input frequencies. Another type is the sample and hold phase detector where a linear representation of the phase of one input signal is instantaneously sampled once per cycle of a second input. The output is maintained by a hold circuit until the next phase sample occurs. A further type is the exclusive-OR phase detector which accepts two square wave digital inputs and provides an exclusive-OR output, proportionate to the phase difference in the inputs. The most widely used phase detector in commercial IC phase-locked loops and frequency synthesizers is the phase-frequency detector. This detector has the highly desirable characteristic of providing both a phase difference signal and a frequency difference signal, which assures frequency acquisition.
Many electronic systems require an accurate frequency reference that can be programmed to one of a number of required values. For example, a FM radio must tune to 87.9 MHz, 88.1 MHz, 88.3 MHz . . . 107.7 MHz, 107.9 MHz. In this case, the radio's receiver must embody a frequency reference that can tune over a 20 MHz range with a step size of 200 KHz. This tuning function is often implemented by a phase locked loop equipped for frequency synthesis. If the PLL is configured for frequency synthesis, it will also include a programmable divider.
FIG. 1 is a simplified block diagram illustrating an example of a typical phase locked loop (PLL) implemented as a frequency synthesizer. FIG. 1 serves as only one example of a PLL and is not limited to the following described elements. The PLL synthesizer comprises a reference signal generator 102, a phase detector 106, a charge pump 108, a low pass filter 110, a voltage controlled oscillator (VCO) 112 and a programmable divider 114. The output of the phase detector is connected to the input of the charge pump. The output of the charge pump (V.sub.p) provides input to the low pass filter 110. The output of the low pass filter is the tuning control voltage (V.sub.t). V.sub.t is the input for VCO 112. The output of the VCO is the synthesized frequency (F.sub.s). F.sub.s is the input for the programmable divider. The programmable divider reduces the frequency F.sub.s by a predetermined amount and outputs this lower frequency signal (F.sub.v). F.sub.v is an input of the phase detector. The other input of the phase detector is the output F.sub.r of reference signal generator. In many frequency synthesizers the reference signal is itself derived from a signal reduced in frequency by a separate divider. A PLL implemented in this manner is known as a frequency synthesizer in that it can produce any number of output frequencies F.sub.s from a single F.sub.r depending on the value of the variable N.
FIG. 2 of the prior art illustrates a more detailed view of some of the elements shown in PLL 100 of FIG. 1. The phase detector 106 accepts as inputs F.sub.r and F.sub.v and provides as outputs an up-line 202 and down-line 204 to current sources 206A and 206B, respectively of charge pump 108. The current sources are connected to supply and ground and provide an input to VCO 112 through a connecting node V.sub.p. If F.sub.r falls before F.sub.v, the up-line 204 is asserted. If F.sub.v falls before F.sub.r the down-line 202 is asserted. The low pass filter 110 is implemented as a passive lag lead filter and comprises capacitors 208A-B, and a resistor 210 which are all connected to ground. Typically, the low pass filter 110 is used to integrate current before it reaches the VCO 112.
The critical node in any phase locked loop is the output node V.sub.p as shown in FIGS. 1-2. As mentioned above, node V.sub.p provides input to the VCO. Ideally, this voltage is purely DC with only error correction information present. However, in practice this goal is not easily achieved. Practical issues can introduce AC voltages, and hence unwanted FM sidebands in the synthesizer. These sidebands interfere with the ability of the PLL to keep F.sub.r and F.sub.v in phase lock. There are three primary causes for the introduction of spurious sidebands into the output of node V.sub.p : charge pump leakage, current source mismatch, and sidebands resulting from the circuitry utilized in PLLs of the frequency synthesizer type.
Charge pump leakage results from the deviation from ideal performance of the components utilized in the charge pump. In charge pump 108 of FIG. 2, at least one of the current sources 206A or 206B has at least one half of the charge pump supply voltage impressed across it. As the current sources are typically constructed with nonideal transistors, this voltage causes leakage current through the transistors when the current sources should ideally be in the OFF state. This leakage current causes the capacitors 208A-B in the low pass filter 110 to charge (or discharge) during the OFF state of the charge pump. This charge is replaced periodically at each phase detector comparison cycle. The charge pump leakage causes a sawtooth waveform on node V.sub.p. This introduces unwanted sidebands in the spectrum of F.sub.s thus resulting in incomplete phase lock. Ideally, a pure DC waveform is desired for node V.sub.p.
The second source of unwanted sidebands in the output of V.sub.p is mismatched current sources. When the frequency and phase of F.sub.v and F.sub.r are equal, the charge pump 108 will output both up and down pulses of current, which are ideally equal and opposite, in order for the net charge injected into the low pass filter to be zero. However, because the Up and Down current sources 206A and 206B are usually constructed from complementary devices with nonsymmetrical characteristics, it is difficult to match the output current pulses rise/fall times and amplitudes. This mismatch results in transient voltage disturbances on output node V.sub.p at the comparison frequency rate, and hence unwanted sidebands in the synthesizer output spectrum and therefore incomplete phase lock.
The final source of undesirable sidebands in the output of node V.sub.p is the fractional division process associated with fractional-N frequency synthesizers. There are two types of division circuitry associated with frequency synthesis. These are called integer-N and fractional-N. In an integer-N divider, a denominator N is variable in integer steps. It follows that the smallest step change in the output frequency would be equal to F.sub.r, and that tuning would only be possible at integer multiples of that F.sub.r. In order to produce much smaller step changes in the output frequency, circuitry known as fractional-N has been devised. There are a number of ways to divide by fractions in fractional-N phase locked synthesizer technology. However, the methods are typically based on the principle of switching the divide ratio of the programmable VCO divider, between different values on successive comparison cycles of the phase detector. For example, a divide ratio of 100.5 could be achieved by alternately switching the programmable VCO denominator between 100 and 101. As the denominator switches output frequency, unwanted sidebands are introduced in the output spectrum of F.sub.s. This can result in less than optimal tracking or signal lock, and is particularly noticeable in systems that require fine frequency resolution and high output frequencies. The sidebands introduced by the fractional division process can not be completely removed by low pass filtering and as a result, the signal phase lock is affected.
Within the limited context of reducing spurious sidebands due to the fractional division process, several conventional approaches exist. One conventional method for fractional sideband compensation is described in U.S. Pat. No. 5,038,120, entitled Frequency Modulated Phase Locked Loop with Fractional Divider and Jitter Compensation, issued to Wheatley et al., which is hereby incorporated by reference. This patent employs a digital accumulator to store the fractional phase error and relies on the fact that the numeric value stored in the accumulator at any time is proportional to the instantaneous systematic phase error. This method uses a digital to analog converter to generate a current that is proportional to the accumulator contents (and hence the systematic phase error). This current is then subtracted from the charge pump output of the phase detector to reduce unwanted sidebands.
Another conventional method for fractional sideband compensation is referred to as a digital spurious reduction. There have been a number of proposals concerning digital timing methods to reduce the fractional sidebands in fractional-N synthesizers. One particular method is described in U.S. Pat. No. 5,124,670, entitled Frequency Synthesizers with Fractional Division, issued to Lawton, which is hereby incorporated by reference. These methods use digital techniques such as, a sigma delta modulation to spread the sideband energy and increase its frequency so that the sideband can be more completely removed by the filter.
Yet another conventional method for fractional sideband compensation is referred to as phase interpolation. Phase interpolation methods recognize that the error in many architectures of fractional-N synthesizers takes a known form. These methods attempt to adjust the phase of the VCO in an open loop circuit that attempts to cancel the known phase error introduced in the division process. One form of this method is described in U.S. Pat. No. 4,206,425, entitled Digitized Frequency Synthesizer, issued to Nossen, which is hereby incorporated by reference.
None of the conventional methods address the elimination of spurious sidebands introduced into node V.sub.p as a result of charge pump leakage or component mismatch. Some of the above mentioned techniques do address the problem of reducing spurious sidebands resulting from fractional-N circuitry, but do so by introducing higher order sidebands.
What is needed is a PLL in which spurious sidebands at the critical node V.sub.p are reduced, and in which the degradation in tracking due to the fractional division process are substantially eliminated.